1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a circuit resistance element which does not contain a parasitic transistor or a parasitic thyristor.
2. Description of the Prior Art
In general, a resistance element, as may be employed in a semiconductor integrated circuit, is made up of a diffused low resistance region, which is formed in a portion of a high resistance semiconductor layer, the region and the layer being of opposite conductivity types. Illustrative examples of this type of resistor element are described in Japanese Pat. application publication No. 10461/1971, corresponding to U.S. application Ser. No. 511,197 No. 30400/1972, No. 38657/1970, No. 18093/1971, and No. 43876/1972. For the examples illustrated in these publications, it is often the case that a p -type base region for a transistor, formed with an n.sup.--type epitaxial layer isolated by a p- type silicon substrate and a p-type diffused isolation region, is employed for the circuit resistance.
For the isolation of the diffused resistance from the substrate, there is one form wherein it is connected to a power voltage source, and another wherein it is placed in a floating state.
More specifically, where a potential below the power source voltage is supplied to the circuit resistance, the p-type region is employed for the circuit resistance and the power voltage is fed to the n-type epitaxial layer. In this case, no problem arises. However, where a voltage above the power source voltage is supplied to the circuit resistance, the p-type region is employed for the circuit resistance and the n-type epitaxial layer is maintained in the state of a so-called "floating island" which is not connected with any other region. In this case, the problems discussed hereinafter may arise.
FIG. 1 illustrates an example of a SEPP circuit, with a bootstrap connection, wherein only a specified portion has a potential greater than a power source voltage. The SEPP Circuit comprises a push-pull output stage P.P., a driving amplifying stage D.C., a bootstrap condenser C.sub.1 and an output coupling condenser C.sub.2. The push-pull output stage P.P. comprises n-p-n transistor Q.sub.1, p-n-p transistor Q.sub.2 and resistors R.sub.3 and R.sub.4. The driving amplifying stage D.C. Comprises n-p-n transistor Q.sub.3, diodes D.sub.1 and D.sub.2 and resistors R.sub.1 and R.sub.2. In this circuit, the voltage which is greater than the power source voltage is applied to the junction A between resistors R.sub.1 and R.sub.2 which are connected to bootstrap capacitor C.sub.1. The device structure for implementing this circuit is as illustrated in FIG. 2, wherein an n.sup.- -type epitaxial layer 2 is the above-referred to "floating island", while a p-type diffused region 4 is employed for resistances R.sub.1 and R.sub.2.
One problem with this type of circuit is the creation of a parasitic ( p- n.sup.- - p.sup.- ) transistor Q.sub.p, illustrated in broken lines in FIG. 1, formed between p- type region 4, n.sup.- epitaxial layer 2 and p.sup.--type substrate 1. Assuming that a leakage current I.sub.CBO appears between the n.sup.- -type epitaxial layer 2 and the p.sup.- -type substrate 4, due to crystal defects in the n.sup.- -type layer 2, the parasitic transistor Q.sub.p will cause a current I.sub.CEO = I.sub.CBO (1 +h.sub.fe ) to flow from the p-type region 4 to the p.sup.- -type substrate 1. The current of the p-type region of resistances R.sub.1 and R.sub.2 will be decreased in accordance with the leakage current I.sub.CEO. As a result, a deviation in the value of the resistance becomes large and the circuit operation deteriorates.
Another problem is the creation of a parasitic thyristor, shown as broken line circuit Spnpn in FIG. 1. Assume, by way of example, that the h.sub.fe of the parasitic ( p-n.sup.- -p.sup.- ) transistor is 50, then the grounded base current gain .alpha. ( p-n-p) of the transistor becomes: ##EQU1##
On the other hand, another parasitic n-p-n transistor is created between n-type epitaxial layer 2, p-type substrate 1 and n-type layer 10 ( an n-type inverted layer which is created in the substrate in such a way that a donor element is mixed into the metal tab (electrode) 11 mounted on the opposite principal plane of the p-type substrate 1 ). Both of these transistors contribute to the formation of the parasitic thyristor ( S-p-n-p-n ). Here, the turn-on condition of the parasitic thyristor is determined by .alpha..sub.pnp of the parasitic pnp transistor and .alpha..sub.npn of the parasitic npn transistor. This condition is defined in accordance with the equation EQU .alpha..sub.pnp + .alpha..sub.npn .gtoreq. 1 (2)
where .alpha..sub.pnp = 0.98 from equation (1) if .alpha..sub.npn is at least equal to 0.02, the thyristor turn-on phenomenon takes place.
In general, in the above npn parasitic transistor, the diffusion concentration of the n-type layer (emitter) is low, and the area of the p-type substrate (face) is very wide. Accordingly, while .alpha. .ltoreq. 0.02, there may arise the case where .alpha. =.apprxeq. 0.2 or greater. When the parasitic thyristor is turned on, the element will be destroyed.